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october 2009 doc id 16324 rev 1 1/69 69 SPEAR300 embedded mpu with arm926 core, flexible memory support, powerful connectivity features and human machine interface features arm926ej-s core up to 333 mhz high-performance 8-channel dma dynamic power-saving features configurable peripheral functions multiplexed on 102 shared i/os memory ? 32 kb rom and 57 kb internal sram ? lpddr-333/ddr2-666 external memory interface ? flexible static memo ry controller (fsmc) up to 16-bit data bus width, supporting external sram, nand/nor flash and fpgas ? serial spi flash interface ? sdio/mmc card interface connectivity ? 2 x usb 2.0 host ? usb 2.0 device ? fast ethernet (mii port) ? spi, i 2 c, i 2 s, uart and irda interfaces ? tdm bus (512 timeslots) ? up to 8 additional i 2 c/spi chip selects security ? c3 cryptographic accelerator peripherals supported ? camera interface (itu-601/656 and csi2 support) ? tft/stn lcd controller (resolution up to 1024 x 768 and up to 24 bpp) ? touchscreen support ? 9 x 9 keyboard controller ? glueless management of up to 8 slics/codecs miscellaneous functions ? integrated real time clock, watchdog, and system controller ? 8-channel 10-bit adc, 1 msps ?1-bit dac ? jpeg codec accelerator ? six 16-bit general purpose timers with capture mode and programmable prescaler ? up to 44 gpios applications SPEAR300 embedded mpu is configurable in 13 sets of peripheral functions targeting a range of applications: ? general purpose nand flash or nor flash based devices ? digital photo frames ? wifi or ip phones (low end or high end) ? ata pabx systems (with or without i 2 s) ? 8-bit or 14-bit camera (with or without lcd) table 1. device summary order code temp range, c package packing SPEAR300-2 - 40 to 85 c lfbga289 (15x15 mm) pitch 0.8 mm tr ay lfbga289 (15 x 15 x 1.7 mm) www. s t.com
contents SPEAR300 2/69 doc id 16324 rev 1 contents 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 architecture overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 arm 926ej-s cpu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 embedded memory units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.3 mobile ddr/ddr2 memory controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.4 serial memory interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.5 sdio/mmc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.6 flexible static memory controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.7 multichannel dma controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.8 clcd controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.9 gpios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.10 jpeg (codec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.11 camera interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.12 cryptographic co-processor (c3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.13 tdm interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.14 i 2 s interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.15 8-channel adc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.16 1-bit dac . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.17 keyboard controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.18 ethernet controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.19 usb2 host controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.20 usb2 device controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.21 ssp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.22 i 2 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.23 uart with irda . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.24 system controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.24.1 power saving system mode control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.24.2 clock and reset system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.24.3 vectored interrupt controller (vic) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.24.4 general purpose timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.24.5 watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
SPEAR300 contents doc id 16324 rev 1 3/69 2.24.6 rtc oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.25 spi_i2c multiple slave control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.1 re q uired external components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.2 dedicated pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.3 shared i/o pins (pl_gpios) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4 memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 5 electrical characteristi cs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 5.1 absolute minimum and maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . 39 5.2 maximum power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 5.3 dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 5.4 overshoot and undershoot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 5.5 general purpose i/o characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 5.6 lpddr and ddr2 pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 5.6.1 ddr2 timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 5.7 clcd timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 5.7.1 clcd timing characteristics direct clock . . . . . . . . . . . . . . . . . . . . . . . . 46 5.7.2 clcd timing characteristics divided clock . . . . . . . . . . . . . . . . . . . . . . . 47 5.8 i 2 c timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 5.9 fsmc timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 5.9.1 8-bit nand flash configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 5.9.2 16-bit nand flash configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 5.10 ether mac 10/100/1000 mbps (gmac-univ) timing characteristics . . . . 54 5.10.1 gmii transmit timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 5.10.2 mii transmit timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 5.10.3 gmii-mii receive timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . 57 5.10.4 mdio timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 5.11 smi - serial memory interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 5.12 spi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 5.12.1 spi master mode timings (clock phase = 0) . . . . . . . . . . . . . . . . . . . . . 62 5.12.2 spi master mode timings (clock phase = 1) . . . . . . . . . . . . . . . . . . . . . 63 5.13 uart (universal asynchronous receiver/transmitter) . . . . . . . . . . . . . . . 65
contents SPEAR300 4/69 doc id 16324 rev 1 5.14 power up se q uence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 5.15 power on reset (mreset) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 6 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 7 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
SPEAR300 description doc id 16324 rev 1 5/69 1 description the SPEAR300 is a member of the spear family of embedded mpus for networked devices. it is based on the powerful arm926ej-s processor (up to 333 mhz), widely used in applications where high computation performance is re q uired. in addition, SPEAR300 has an mmu that allows virtual memo ry management -- making the system compliant with linux operating system. it also offers 16 kb of data cache, 16 kb of instruction cache, jtag and etm (embedded trace macro-cell) for debug operations. a full set of peripherals allows the system to be used in many applications, some typical applications being hmi, security and voip phones. figure 1. functional block diagram

description SPEAR300 6/69 doc id 16324 rev 1 main features: arm926ej-s 32-bit risc cpu, up to 333 mhz ? 16 kbytes of instruction cache, 16 kbytes of data cache ? 3 instruction sets: 32-bit for high performance, 16-bit (thumb) for efficient code density, byte java mode (jazelle?) for direct execution of java code. ? tightly coupled memory ? amba bus interface 32-kbyte on-chip bootrom 57-kbyte on-chip sram 16-bit mobile ddr/ddr2 memory controller (up to 333 mhz) serial memory interface sdio/mmc interface supporting spi, sd1, sd4 and sd8 mode with card detect, write protect, led 8/16-bits nor flash/nand flash controller boot capability from nand flash, serial /parallel nor flash, ethernet and uart boot and field upgrade capability from usb multichannel dma controller color lcd controller for stn/tft display panels ? up to 1024 x 768 resolution ? 24 bpp true color up to 44 gpios (muxed with peripheral i/os), up to 22 with interrupt capability jpeg codec accelerator, 1 clock/pixel camera interface itu-601 with external or embedded synchronization (itu-656 or csi2). picture limit is given by the line length that must be stored in a 2048 x 32 buffer c3 crypto accelerato r (des/3des/aes/sha1) tdm master/slave ? up to 512 timeslots ? any input timeslot can be switched to any output timeslot, and/or can be buffered for computation ? up to 16 channels of 1 to 4 timeslots buffered during 32 ms ? up to 16 buffers can be played in output timeslots i 2 s interface, full duplex with data buffer for left and right channels allowing up to 64 ms of voice buffer (for 32 bit samples). 10-bit adc, 1 msps, 8 inputs/1-bit dac 9 x 9 keyboard controller ethernet mac 10/100 mbps (mii phy interface) two usb2.0 host (high- full-low speed) with in tegrated phy transceiver one usb2.0 device (high-full-low speed) with integrated phy transceiver spi master/slave (motorola, texas instruments, national semiconductor protocols) up to 50 mbps i 2 c (slow- fast-high speed, up to 1.2 mb/s) master/slave i/o peripherals ? uart (speed rate up to 460.8 kbps)
SPEAR300 description doc id 16324 rev 1 7/69 ? irda (fir/mir/sir) 9.6 kbps to 4 mbps speed-rate advanced power saving features ? normal, slow, doze and sleep modes cpu clock with software-programmable fre q uency ? enhanced dynamic power-domain management ? clock gating functionality ?low fre q uency operating mode ? automatic power saving controlled from application activity demands vectored interrupt controller system and peripheral controller ? 3 pairs of 16-bit general purpose timers with programmable prescaler. ? rtc with separate power supply allowing battery connection ? watchdog timer ? miscellaneous registers array for embedded mpu configuration programmable pll for cpu and system clocks jtag ieee 1149.1 boundary scan etm9 interface and embedded ice-rt etm functionality multiplexed on primary pins supply voltages ? 1.2 v core, 1.8 v to 3.3 v i/os operating temperature: - 40 to 85 c lfbga289 (15 x15 mm, pitch 0.8 mm)
architecture overview SPEAR300 8/69 doc id 16324 rev 1 2 architecture overview the SPEAR300 internal architec ture is based on several s hared subsystem logic blocks interconnected through a multilayer interconnection matrix. the switch matrix structure allows different subsystem dataflow to be executed in parallel improving the core platform efficiency. high performance master agents are directly interconnected with the memory controller reducing the memory access latency. the overall memory bandwidth assigned to each master port can be programmed and optimized through an internal efficient weighted round- robin arbitration mechanism. figure 2. SPEAR300 overview 2.1 arm 926ej-s cpu the SPEAR300 cpu is an arm926 ej reduced instruction set co mputer (risc) processor. it supports the 32-bit arm and 16-bit thumb instruction sets, enabling the user to trade off between high performance and high code density and includes features for efficient execution of java byte codes. the arm cpu and is clocked at a fre q uency up to 333 mhz. it has a 16-kbyte instruction cache, a 16-kbyte data cache, and features a memory management unit (mmu) which makes it fully compliant with linux and vxworks operating systems. it also includes an embedded trace module (etm medium+) for real-time cpu activity tracing and debugging. it supports 4-bit and 8-bit normal trace mode and 4-bit demultiplexed trace mode, with normal or half-rate clock.

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SPEAR300 architecture overview doc id 16324 rev 1 9/69 2.2 embedded memory units 32 kbytes of bootrom 57 kbytes of sram 2.3 mobile ddr/ddr2 memory controller SPEAR300 integrates a high performances multi- channel memory contro ller able to support low power mobile ddr and ddr2 double data rate memory devices. the multi-port architecture ensures memory is shared efficiently among different high-bandwidth client modules. it offers 6 internal ports. one of them is reserved for register access during the controller initialization while the other five are used to access the external memory. it also include the physical layer (phy) and some dlls that allow fine tuning of all the timing parameters to maximize the data valid windows at any fre q uency in the allowed range. 2.4 serial memory interface the main features of smi are listed below: supports the following spi-comp atible flash and eeprom devices: ? stmicroelectronics m25pxxx, m45pxxx ? stmicroelectronics m95xxx, except m95040, m95020 and m95010 ?atmel at25fxx ?ymc y25fxx ? sst sst25lfxx acts always as a spi master and up to 2 spi slave memory devices are supported (through as many chip select signals), with up to 16 mb address space each smi clock signal (smiclk) is generated by smi (and input to all slaves) using a clock provided by the ahb bus smiclk can be up to 50 mhz in fast read mode (or 20 mhz in normal mode). it can be controlled by 7 programmable bits. 2.5 sdio/mmc SPEAR300 provides an sdio host controller th at has an amba compatible interface and conforms to the sd host controller standard specification version 2.0. it handles sd/sdio protocol at transmission level, packing data, adding cyclic redundancy check (crc), start/end bit, and checking for transaction format correctness.
architecture overview SPEAR300 10/69 doc id 16324 rev 1 main features: meets the following standard specifications: ? sd host controller standard specification version 2.0 ? sdio card specification version 2.0 ? sd memory card specification draft version 2.0 ? sd memory card security specification version 1.01 ? mmc specification version 3.31 and 4.2 supports both dma and non-dma mode of operation supports mmc plus and mmc mobile card detection (insertion/removal) password protection of cards host clock rate variable between 0 and 48 mhz supports 1-bit, 4-bit and 8-bit sd modes and spi mode supports multimedia card interrupt mode allows card to interrupt host in 1-bit, 4-bit, 8-bit sd modes and spi mode. up to 100 mbit/s data rate using 4 parallel data lines (sd4-bit mode) up to 416 mbit/s data rate using 8-bit parallel data lines (sd8-bit mode) cyclic redundancy check crc7 for command and crc16 for data integrity designed to work with i/o cards, read-only cards and read/write cards error correction code (ecc) support for mmc4.2 cards supports read wait control, suspend/resume operation supports fifo overrun and underrun condition by stopping the sd clock conforms to amba specification ahb (2.0)
SPEAR300 architecture overview doc id 16324 rev 1 11/69 2.6 flexible static memory controller SPEAR300 provides a flexible static memory controller (fsmc) whic h interface the ahb bus to external nand/nor flash memories and to asynchronous sram memories. main features: provides an interface between ahb system bus and external parallel memory devices interfaces static memory-mapped devices including ram, rom and synchronous burst flash. for sram and flash 8/16-bit wide, external memory and data paths are provided fsmc performs only one access at a time and only one external device is accessed. supports little-endian and big-endian memory architectures ahb burst transfer handling to reduce access time to external devices supplies an independent configuration for each memory bank programmable timings to support a wide range of devices programmable wait states (up to 31) programmable bus turnar ound cycles (up to 15) programmable output enable and write enable delays (up to 15) provides independent chip select control for each memory bank shares the address bus and the data bus with all the external peripherals. only the chip selects are uni q ue for each peripheral external asynchronous wait control boot memory bank configurable at reset using external control pins 2.7 multichannel dma controller within its basic subs ystem, SPEAR300 provides an dma controller (dmac) able to service up to 8 independent dma channels for serial data transfers between single source and destination (i.e., memory-to-memory, memory-to-peripheral, peripheral to- memory, and peripheral-to-peripheral). each dma channel can support a unidirectional transfer, with internal four-word fifo per channel.
architecture overview SPEAR300 12/69 doc id 16324 rev 1 2.8 clcd controller SPEAR300 has a color li q uid crystal display controller (c lcdc) that provides all the necessary control signals to interface directly to a variety of color and monochrome lcd panels. main features: resolution programmable up to 1024 x 768 16-bpp true-color non-palletized, for color stn and tft 24-bpp true-color non-palletized, for color tft supports single and dual panel mono super twisted nematic (stn) displays with 4 or 8- bit interfaces supports single and dual-panel color and monochrome stn displays supports thin film transistor (tft) color displays 15 gray-level mono, 3375 color stn, and 32 k color tft support 1, 2, or 4 bits per pixel (bpp) palletized displays for mono stn 1, 2, 4 or 8-bpp palletized color displays for color stn and tft programmable timing for different display panels 256 entry, 16-bit palette ram, arranged as a 128 x 32-bit ram physically frame, line and pixel clock signals ac bias signal for stn and data enable si gnal for tft panels patented gray scale algorithm supports little and big-endian 2.9 gpios the general purpose input/outputs (gpios) provide programmable inputs or outputs. each input/output can be controlled in two distinct modes: software mode, through an apb interface hardware mode, through a hardware control interface. main features: up to 44 individually programmable input/output pins implemented in 4 blocks: ? up to 6 base gpios in the basic subsystem (basgpio) ? up to 18 gpios in the telecom subsystem (g10 and g8) ? up to 8 gpios in the independent gpio block (gpio[7:0]) ? other gpios available on free pl_gpio pins in the ras block. programmable interrupt generati on capability up to 22 pins. base gpios and independent gpios support bit masking in both read and write operation through address lines.
SPEAR300 architecture overview doc id 16324 rev 1 13/69 2.10 jpeg (codec) SPEAR300 provides a jpeg codec with header processing (jpgc), able to decode (or encode) image data contained in the ram memory, from the jpeg (or bmp) format to the bmp (or jpeg) format. main features: compliance with the baseline jpeg standard (iso/iec 10918-1) single-clock per pixel encoding/decoding support for up to four channels of component color 8-bit/channel pixel depths programmable q uantization tables (up to four) programmable huffman tables (two ac and two dc) programmable minimum coded unit (mcu) configurable jpeg headers processing support for restart marker insertion use of two dma channels and of two 8 x 32-bits fifo?s (local to the jpeg) for efficient transferring and buffering of encoded/decoded data from/to the codec core. 2.11 camera interface the camera interface receives data from a sensor in parallel mode (8 to 14-bits) by storing a full line in a buffer memory, then re q uesting a dma transfer or interrupting the processor. when all the lines of a frame are transferred, a frame sync interrupt is generated. main features: supports both hardware synchronization (hsync and vsync signals) and embedded synchronization (itu656 or csi2). data carried by the bus can be: ? raw bayer10 (10-14 bits/pixel ? 2 bytes), raw bayer8 (8 bits/pixel ? 1 byte), ? ycbcr400 (1 byte/pixel ? 1 byte), ycbcr422 (4 bytes/ 2 pixels ? 2*2 bytes), ycbcr444 (3 bytes/ pixel ? 4 bytes) ? rgb444 (2 bytes/ pixel ? 2 bytes), rgb565 (2 bytes/ pixel ? 2 bytes), rgb888 (3 bytes/ pixel ? 4 bytes) ? jpeg compressed data is stored in a 2048 x 32 buffer memory the camera interface can be assigned to two different set of pins. when using data greater than 8-bits, it is not possible to use the mii interface. max pixel clock fre q uency is 100 mhz
architecture overview SPEAR300 14/69 doc id 16324 rev 1 2.12 cryptographic co-processor (c3) main features: supported cryptographic algorithms: ? advanced encryption sta ndard (aes) cipher in ecb, cbc, ctr modes ? data encryption standard (des) cipher in ecb and cbc modes. ? sha-1, hmac-sha-1, md5, hmac-md5 digests. instruction driven dma based programmable engine. ahb master port for data access from/to system memory. ahb slave port for co-processor regi ster accesses and in itial engine-setup the co-processor is fully autonomous (dma input reading, cryptographic operation execution, dma output writing) after being set up by the host processor the co-processor executes programs written by the host in memory, it can execute an unlimited list of programs. the co-processor supports hardware chaining of cryptographic blocks for optimized execution of data-flow re q uiring multiple algorithms processing over the same set of data (for example encryption + hashing on the fly)
SPEAR300 architecture overview doc id 16324 rev 1 15/69 2.13 tdm interface the tdm block implements time division multiplexing. main features: tdm interface with 512 timeslots and up to 16 bufferization channels. 32 ms bufferization for 16 channels (of 4 bytes each) supports master and slave mode operation programmable clock and synchronization signal generation in master mode clock & synchronization signal recovery in slave mode 8 programmable synchronization signals for codecs uses 11 pins: ? sync7-0 are dedicated frame syncs for codecs without timeslot recognition ? clk is the tdm clock ? din is the tdm input and receives the data ? dout is the tdm output and transmits the data. it can be high impedance on a unused timeslot the tdm interface can be the master or a slave of the clk or sync0 signals. timeslots can be used for switch ing or bufferization purposes: ? switching and bufferization can be used concurrently for different timeslots on the same tdm ? the only limitation is that an output timeslot can not be switched and bufferized at the same time. ? timeslot switching: any of the output time slots can receive any input timeslot of the previous frame. the connection memory is part of the action memory, indicating which timeslot has to be output. ? timeslot bufferization: data from din is stored in an input buffer and data from an output buffer is played on dout. when the number of samples stored/played reaches the buffer size, the processor is interrupted in order to read the input buffer and prepare a new output buffer (or a dma re q uest is generated). 2.14 i 2 s interface the i 2 s interface is very similar to the tdm block, but the frame sync is limited to philips i 2 s definition. it is composed of 4 signals: i2s_lrck; left and right channels synchronization (master/slave) i2s_clk: i 2 s clock (master/slave) i2s_din: i 2 s clock (master/slave) i2s dout: i 2 s output (tri-state) the dout line can be high impedance when out of samples. data is always stored in 32 bit format in the buffer. a shift left operation is possible to left align the data.
architecture overview SPEAR300 16/69 doc id 16324 rev 1 main features: can be master or slave for the clock and sync signals buffering of up to 1024 samples (512 left and 512 right samples representing 64 ms of voice). data is stored always on 32 bits. left and right channels are stored in two different buffers. two banks are used to exchange data with the processor. in master mode, lrck can be adjusted for 8, 16 or 32 bits width. data width can be less than lrck width. input (received on i2s_din) and output (transmitted on dout) can be 8, 16 or 32 bits. 2.15 8-channel adc main features: successive approximatio n conversion method 10-bit resolution @1 msps hardware supporting up to 13.5 bits resolution at 8 ksps by oversampling and accumulation eight analog input (ain) channels, ranging from 0 to 2.5 v inl 1 lsb, dnl 1 lsb programmable conversion speed, (min. conversion time is 1 s) programmable average results from 1 (no averaging) up to 128 programmable auto scan for all the eight channels. normal or enhanced mode; ? in normal mode the conversion start upon cpu re q uest ? in enhanced mode the adc converts continuously the selected channels inserting a selectable amount of time between two conversions. 2.16 1-bit dac the one-bit dac is a second-order noise shaper based on the tdm hardware. the action memory determines whether a new sample needs to be sent to the dac during the next byte. samples are read from the buffer memory. main features: input data must be 32-bits wide, either in 2?s complement or binary form. oversampling min 32, max 256 s/n ratio is 82 db, thd is 72 db (measured on a 1 khz sine wave x64 over sampled by the processor and x32 by the dac) dynamic: 80% of full scale optionally, the order of the noise shaper can be set to 1
SPEAR300 architecture overview doc id 16324 rev 1 17/69 2.17 keyboard controller SPEAR300 provides a gpio/keyboard block wh ich is a two-mode in put and output port. main features: the selection between the two modes is an apb bus programmable bit. keyboard interface uses 18 pins 18-bit general-pur pose parallel port with input or output single pin programmability pins can be either used as standard gpios or to drive a 9 x 9 keyboard (81 keys) keyboard scan period can be adjusted between 10 ms and 80 ms supports auto-scanning with debouncing. 2.18 ethernet controller main features: compliant with the ieee 802.3-2002 standard supports the default mii interface to the external phy supports 10/100 mbps data transfer rates local fifo available (4 kbyte rx, 2 kbyte tx) supports both half-duplex and full-duplex operation. in half-duplex operation, csma/cd protocol is provided for, as well as packet bursting and frame extension at 100 mbps programmable frame length to support both standard and jumbo ethernet frames with size up to 16 kbyte a variety of flexible addresses filtering modes are supported a set of control and status registers (csrs) to control gmac core operation native dma with single-channel transmit and receive engines, providing 32/64/128-bit data transfers dma implements dual-buffer (ring) or linked-list (chained) descriptor chaining an ahb slave acting as programming interface to access all csrs, for both dma and gmac core subsystems an ahb master for data transfer to system memory 32-bit ahb master bus width, supporting 32, 64, and 128-bit wide data transactions it supports both little and big endian memory architectures 2.19 usb2 host controller spear 300 has two fully independent usb 2.0 hosts. each one is constituted by 5 major blocks: ehci capable of managing high-speed transfers (hs mode, 480 mbps) ohci that manages the full and the low speed transfers (12 and 1.5 mbps) local 2-kbyte fifo local dma integrated usb2 transceiver (phy)
architecture overview SPEAR300 18/69 doc id 16324 rev 1 both hosts can manage an external power switch, providing a control line to enable or disable the power, and an input line to sense any over-current condition detected by the external switch. one host controller at time can perform high speed transfer. 2.20 usb2 device controller the usb2 device controller pr ovides the following features: supports the 480 mbps high-speed mode (hs) for usb 2.0, as well as the 12 mbps full-speed (fs) and the low-speed (ls modes) for usb 1.1 supports 16 physical endpoints, which can be assigned to different interfaces and configurations to implement logical endpoints integrated usb transceiver (phy) local 4 kbyte fifo shared by all endpoints dma mode and slave-only mode are supported in dma mode, the udc supports descriptor-based memory structures in application memory in both modes, an ahb slave is provided by udc-ahb, acting as programming interface to access to memory-mapped control and status registers (csrs) an ahb master for data transfer to system memory is provided, supporting 8, 16, and 32-bit wide data transactions on the ahb bus a usb plug detect (upd) which detects the connection of a cable. 2.21 ssp SPEAR300 provides one sync hronous serial port (ssp) block that offers a master or slave interface for synchronous serial communication with slave or master peripherals main features: maximum speed of 41.5 mbps master and slave mode capability programmable clock bit rate and prescale separate transmit and receive first-in, first-out memory buffers, 16 bits wide, 8 locations deep programmable choice of interface operation: ? spi (motorola) ? microwire (national semiconductor) ? ti synchronous serial programmable data frame size from 4 to 16-bit. independent masking of transmit fifo, receive fifo, and receive overrun interrupts dma interface
SPEAR300 architecture overview doc id 16324 rev 1 19/69 2.22 i 2 c the i2c controller, acts as an apb slave interface to the two-wire serial i2c bus. main features: compliance to the i2c-bus specification (philips) i 2 c v2.0 compatible. operates in three different speed modes: ? standard (100 kbps) ? fast (400 kbps) ? high-speed (3.4 mbps) master and slave mode configuration possible 7-bit or 10-bit addressing 7-bit or 10-bit combined format transfers slave bulk data transfer capability. connection with general purpose dma is provided to reduce the cpu load. interrupt or polled-mode operation supports apb data bus widths of 8, 16 and 32-bits 2.23 uart with irda main features: can be used as uart with software flow control or as an irda interface irda compliant serial link (fir/mir/sir) from 9.6 kbps to 4 mbps speed-rate. separate 16x8 (16 locations deep x 8-bit wide) transmit and 16 x 12 receive fifos to reduce cpu interrupts speed up to 460.8 kbps. 2.24 system controller the system controller provides an interface for controllin g the operation of the overall system. main features: power saving system mode control crystal oscillator and pll control configuration of system response to interrupts reset status capture and soft reset generation watchdog and timer module clock enable remap control general purpose peripheral control r system and peripheral clock control and status
architecture overview SPEAR300 20/69 doc id 16324 rev 1 2.24.1 power saving system mode control using three mode control bits, the system controller switch th e SPEAR300 to any one of four different modes: doze, sleep, slow and normal. sleep mode : in this mode the system clocks, hclk and clk, are disabled and the system controller clock sclk is driven by a low speed oscillator (n ominally 32768 hz). when either a fiq or an irq interrupt is generated (through the vic) the system enters doze mode. additionally, the operating mode setting in the system control register automatically changes from sleep to doze. doze mode : in this mode the system clocks , hclk and clk, and the system controller clock sclk are driven by a lo w speed oscillator. t he system controller moves into sleep mode from doze mode on ly when none of th e mode control bits are set and the processor is in wait-for-interrupt state. if slow mode or normal mode is re q uired the system moves into the xtal co ntrol transition stat e to initialize the crystal oscillator. slow mode : during this mode, both the system clocks and the system controller clock are driven by the crystal oscillator. if normal mode is selected, the system goes into the "pll control" transition state. if neither the slow nor the normal mode control bits are set, the system goes into the "switch from xtal" transition state. normal mode : in normal mode, both the system clocks and the system controller clock are driven by the pll output. if the normal mode control bit is not set, then the system goes into the "switch from pll" transition state. 2.24.2 clock and reset system the clock system is a fully programmable block that generates all the clocks for the SPEAR300. the default operating clock fre q uencies are: clock @ 333 mhz for the cpu. clock @ 166 mhz for ahb bus and ahb peripherals clock @ 83 mhz for, apb bus and apb peripherals clock @ 333 mhz for ddr memory interface. the above fre q uencies are the maximum allowed values. the clock fre q uencies can be modified by programming the clock system registers. the clock system consists of 2 main parts: a multi clock generator bl ock and two internal plls. the multi clock generator block, takes a reference signal (which is usually delivered by the pll), generates all clocks fo r the ips of SPEAR300 accordin g to dedicated programmable registers. each pll uses an oscillator input of 24 mhz to generate a clock signal at a fre q uency corresponding to the highest of the group. this is the reference signal used by the multi clock generator block to obtain all the other re q uired clocks for the group. its main feature is electromagnetic in terference reduct ion capability. the user can set up the pll in order to modulate the vco with a triangular wave. the resulting signal has a spectrum (and power) spread over a small programmable range of fre q uencies centered on f0 (the vco fre q uency), obtaining minimum electromagnetic emissions. this method replaces all the other traditional methods of emi reduction, such as
SPEAR300 architecture overview doc id 16324 rev 1 21/69 filtering, ferrite beads, chokes, adding power layers and ground planes to pcbs, metal shielding and so on. this gives the customer appreciable cost savings. in sleep mode the SPEAR300 runs with the pll disabled so the available fre q uency is 24 mhz or a sub-multiple (/2, /4, /8). 2.24.3 vectored interrupt controller (vic) the vic allows the os interrupt handler to q uickly dispatch interrupt service routines in response to peripheral interrupts. there are 32 interrupt lines and the vic uses a separate bit position for each interrupt source. software controls each re q uest line to generate software interrupts. 2.24.4 general purpose timers SPEAR300 provides three gener al purpose timers (gpts) acting as apb slaves. each gpt consists of 2 channels, each one made up of a programmable 16-bit counter and a dedicated 8-bit timer clock prescaler. the programmable 8-bit prescaler performs a clock division by 1 up to 256, and different input fre q uencies can be chos en through SPEAR300 configuration registers (fre q uencies ranging from 3.96 hz to 48 mhz can be synthesized). two different modes of operation are available: auto-reload mode, an interrupt source is activated, the counter is automatically cleared and then it restarts incrementing. single-shot mode, an interrupt source is activated, the counter is stopped and the gpt is disabled. 2.24.5 watchdog timer the arm watchdog module consists of a 32-bit down counter with a programmable timeout interval that has the capability to generate an interrupt and a reset signal on timing out. the watchdog module is intended to be used to apply a reset to a system in the event of a software failure. 2.24.6 rtc oscillator the rtc provides a 1-second resolution clock. this keeps time when the system is inactive and can be used to wake the system up when a programmed alarm time is reached. it has a clock trimming feature to compensate for the accuracy of the 32.768 khz crystal and a secured time update.
architecture overview SPEAR300 22/69 doc id 16324 rev 1 2.25 spi_i2c multiple slave control the spi interface has only one slave select signal, ss0. the i 2 c interface does not allow control of several devices with the same address, which is fre q uently re q uired for codecs. the spi_i2c extension allows management of up to 8 spi devices, or 8 i 2 c devices at the same address (total spi+i 2 c devices=8). the spi extension is made by generating three more slave select signals ss1, ss2 and ss3. the i 2 c extension is done by replicating the i2c_scl signal if the corresponding pin is set active.otherwise the pin remains low, so that the start condition is not met. each of the 8 pins can reproduce either the spi ss0 signal, or the i2c_scl signal. the selection is made through a register.
SPEAR300 pin description doc id 16324 rev 1 23/69 3 pin description the following tables describe the pinout of the SPEAR300 listed by functional block. list of abbreviations: pu = pull up pd = pull down 3.1 required external components 1. ddr_comp_1v8: place an external 121 k resistor between ball p4 and ball r4 2. usb_tx_rtune: connect an external 43.2 k pull-down resistor to ball k5 3. digital_rext: place an external 121 k resistor between ball g4 and ball f4. 3.2 dedicated pins table 2. master clock, rtc, reset and 3.3 v comparator pin descriptions group signal name ball direction function pin type master clock mclk_xi p1 input 24 mhz (typical) crystal in oscillator 2.5 v capable mclk_xo p2 output 24 mhz (typical) crystal out rtc rtc_xi e2 input 32 khz crystal in oscillator 1v capable rtc_xo e1 output 32 khz crystal out reset mreset# m17 input main reset ttl schmitt trigger input buffer, 3.3 v tolerant, pu 3.3 v comp. digital_rext g4 output configuration analog, 3.3 v capable digital_gnd_r ex f4 power power power table 3. power supply pin description group signal name ball value digital ground gnd g6, g7, g8, g9, g10, g11, h6, h7, h8, h9, h10, h11, j6, j7, j8, j9, j10, j11, k6, k7, k8, k9, k10, k11, l6, l7, l8, l9, l10, m8, m9, m10 0 v analog ground agnd f2, g1, j2, l1, l3, l5, n2, n4, p3, r3,n12 0 v i/o vdd3 f5, f6, f7, f10, f11, f12, g5, j12, k12, l12, m12 3.3 v
pin description SPEAR300 24/69 doc id 16324 rev 1 core vdd f8, f9, g12, h5, h12, j5, l11, m6, m7, m11 1.2 v usb host0 phy host0_vddbc l2 2.5 v host0_vddb3 k4 3.3 v host0_vddbs m3 1.2 v usb host 1 phy host1_vddbc k3 2.5 v host1_vddb3 j1 3.3 v host1_vddbs m3 1.2 v usb device phy device_vddbc n1 2.5 v device_vddb3 n3 3.3 v host0_vddbs m3 1.2v osci (master clock) mclk_vdd r1 1.2v mclk_vdd2v5 r2 2.5 v pll1 dith1_avdd g2 2.5 v pll2 dith2_avdd m4 2.5 v ddr i/o sstl_vdde m5, n5, n6, n7, n8, n9, n10, n11 1.8 v adc adc_avdd n13 2.5 v osci rtc rtc vdd f1 1.5 v table 4. debug pin descriptions group signal name ball direction function pin type debug test_0 k16 input test configuration ports. for functional mode, they have to be set to zero. ttl input buffer, 3.3 v tolerant, pd test_1 k15 test_2 k14 test_3 k13 test_4 j15 boot_sel j14 ntrst l16 input test reset input ttl schmitt trigger input buffer, 3.3 v tolerant, pu tdo l15 output test data output ttl output buffer, 3.3 v capable 4 ma tck l17 input test clock ttl schmitt trigger input buffer, 3.3 v tolerant, pu tdi l14 input test data input tms l13 input test mode select table 3. power supply pin description group signal name ball value
SPEAR300 pin description doc id 16324 rev 1 25/69 table 5. serial memory interface (smi) pin description group signal name ball direction function pin type smi smi_datain m13 input serial flash input data ttl input buffer 3.3 v tolerant, pu smi_dataout m14 output serial flash output data ttl output buffer 3.3 v capable 4 ma smi_clk n17 i/o serial flash clock smi_cs_0 m15 output serial flash chip select smi_cs_1 m16
pin description SPEAR300 26/69 doc id 16324 rev 1 table 6. usb pin descriptions group signal name ball direction function pin type usb dev dev_dp m1 i/o usb device d+ bidirectional analog buffer 5 v tolerant dev_dm m2 usb device d- dev_vbus g3 input usb device vbus ttl input buffer 3.3 v tolerant, pd host1_dp h1 i/o usb host1 d+ bidirectional analog buffer 5 v tolerant host1_dm h2 usb host1 d- usb host host1_vbus h3 output usbhost1 vbus ttl output buffer 3.3 v capable, 4 ma host1_ovrc j4 input usb host1 over-current ttl input buffer 3.3 v tolerant, pd host0_dp k1 i/o usb host0 d+ bidirectional analog buffer 5 v tolerant host0_dm k2 usb host0 d- host0_vbus j3 output usb host0 vbus ttl output buffer 3.3 v capable, 4 ma host0_ovrc h4 input usb host0 over-current ttl input buffer 3.3 v tolerant, pd usb_txrtune k5 output reference resistor analog usb_analog_t est l4 output analog test output analog table 7. adc pin description group signal name ball direction function pin type adc ain_0 n16 input adc analog input channel analog buffer 2.5 v tolerant ain_1 n15 ain_2 p17 ain_3 p16 ain_4 p15 ain_5 r17 ain_6 r16 ain_7 r15 adc_vrefn n14 adc negative voltage reference adc_vrefp p14 adc positive voltage reference
SPEAR300 pin description doc id 16324 rev 1 27/69 table 8. ddr pin description group signal name ball direction function pin type ddr ddr_add_0 t2 output address line sstl_2/sstl_18 ddr_add_1 t1 ddr_add_2 u1 ddr_add_3 u2 ddr_add_4 u3 ddr_add_5 u4 ddr_add_6 u5 ddr_add_7 t5 ddr_add_8 r5 ddr_add_9 p5 ddr_add_10 p6 ddr_add_11 r6 ddr_add_12 t6 ddr_add_13 u6 ddr_add_14 r7 ddr_ba_0 p7 output bank select ddr_ba_1 p8 ddr_ba_2 r8 ddr_ras u8 output row add. strobe ddr_cas t8 output col. add. strobe ddr_we t7 output write enable ddr_clken u7 output clock enable ddr_clk_p t9 output differential clock differential sstl_2/sstl_18 ddr_clk_n u9
pin description SPEAR300 28/69 doc id 16324 rev 1 ddr ddr_cs_0 p9 output chip select sstl_2/sstl_18 ddr_cs_1 r9 ddr_odt_0 t3 i/o on-die termination enable lines ddr_odt_1 t4 ddr_data_0 p11 i/o data lines (lower byte) ddr_data_1 r11 ddr_data_2 t11 ddr_data_3 u11 ddr_data_4 t12 ddr_data_5 r12 ddr_data_6 p12 ddr_data_7 p13 ddr_dqs_0 u10 output lower data strobe differential sstl_2/sstl_18 ddr_ndqs_0 t10 ddr_dm_0 u12 output lower data mask sstl_2/sstl_18 ddr_gate_0 r10 i/o lower gate open ddr_data_8 t17 i/o data lines (upper byte) ddr_data_9 t16 ddr_data_10 u17 ddr_data_11 u16 ddr_data_12 u14 ddr_data_13 u13 ddr_data_14 t13 ddr_data_15 r13 ddr_dqs_1 u15 i/o upper data strobe differential sstl_2/sstl_18 ddr_ndqs_1 t15 ddr_dm_1 t14 i/o upper data mask sstl_2/sstl_18 ddr_gate_1 r14 upper gate open ddr_vref p10 input reference voltage analog ddr_mem_com p_gnd r4 power return for ext. resistors power ddr_mem_com p_rext p4 power ext. resistor analog ddr2_en j13 input configuration ttl input buffer 3.3 v tolerant, pu table 8. ddr pin description (continued) group signal name ball direction function pin type
SPEAR300 pin description doc id 16324 rev 1 29/69 3.3 shared i/o pins (pl_gpios) the 98 pl_gpio and 4 pl_clk pins have the following characteristics: ? output buffer: ttl 3.3 v capable up to 10 ma ? input buffer: ttl, 3.3 v tolerant, select able internal pull up/pull down (pu/pd) configuration modes 13 configurations are available selected by ras control register 2. the peripherals available in each configuration are shown in table 9: available peripheral s in each configuration mode details of each pl_gpio pin are given for each mode in table 10: pl_gpio pin de s cription on page 31 configuration 1 is the default mode for SPEAR300. it supports the fsmc interface for nand flash connectivity and boot pins used for selecting the boot mode. alternate functions other peripheral functions are listed in the alternate functions column of ta bl e 1 0 : pl_gpio pin de s cription and can be individually enabled/disabled via ras control register 1. refer to the user manual for the register descriptions. gpios unused pl_gpio pins can be configured individually in the ras registers to provide additional gpios. the total number of gpio can be up to 44 depending on the configuration mode and the number of alternate functions enabled.
pin description SPEAR300 30/69 doc id 16324 rev 1 tdm interfacing using gpios in some configuration modes where less than 8 tdm devices are indicated in ta b l e 9 , additional tdm devices can be supported by using gpio pins. the tdm needs a dedicated interrupt line, an spi and an independent frame sync signal to interface each device. when enough spi chip selects signals are not available (spi_i2c signals), the chip select can be performed by a gpio. in this case the number of possible tdm devices supported is: modes 5, 7, 8 and 9: up to 8 devices modes 3 and 10: up to 6 devices modes 11 and 12: up to 4 devices table 9. available peripherals in each configuration mode modes fsmc boot pins spi/i2c multi slave control i2s clcd dac camera interface tdm no of voice devices sdio/mmc data lines gpios keyboard keys interrupt pins 1 16-bit nand 4 2 16-bit nor 4 3 16-bit nand 1 18 14 + 8 i/os with its 4 81 1 88149*98 5 4111 28149*9 6 81 1 88149*98 7 4111 28149*9 8 8-bit nor 8 8418 8 9 8-bit nand /nor 81 1 4418 8 10 41 18-bit2889*9 11 11114-bit2887*5 12 1 1 14-bit 2 8 8 7*5 13 41118-bit2849*9
SPEAR300 pin description doc id 16324 rev 1 31/69 table 10. pl_gpio pin description pl / pin number alternate function (enabled by ras register 1) configuration mode (enabled by ras register 2) 12345678910111213 97/h16 /e1 /e1 /e11111 /e1 /e11111 96/h15 d0 dq0 d0 col0 col0 col0 col0 d0 d0 col0 col0 col0 col0 95/h14 d1 dq1 d1 col1 col1 col1 col1 d1 d1 col1 col1 col1 col1 94/h13 d2 dq2 d2 col2 col2 col2 col2 d2 d2 col2 col2 col2 col2 93/g17 d3 dq3 d3 col3 col3 col3 col3 d3 d3 col3 col3 col3 col3 92/g16 d4 dq4 d4 col4 col4 col4 col4 d4 d4 col4 col4 col4 col4 91/g15 d5 dq5 d5 col5 col5 col5 col5 d5 d5 col5 dio0_1 dio0_1 col5 90/g14 d6 dq6 d6 col6 col6 col6 col6 d6 d6 col6 dio1_1 dio1_1 col6 89/f17 d7 dq7 d7 col7 col7 col7 col7 d7 d7 col7 dio2_1 dio2_1 col7 88/f16 d8 dq8 d8 col8 col8 col8 col8 g8_0 g8_0 col8 dio3_1 dio3_1 col8 87/g13 d9 dq9 d9 row0 row0 row0 row0 g8_1 g8_1 row0 row0 row0 row0 86/e17 d10 dq10 d10 row1 row1 row1 row1 g8_2 g8_2 row1 row1 row1 row1 85/f15 d11 dq11 d11 row2 row2 row2 row2 g8_3 g8_3 row2 row2 row2 row2 84/d17 d12 dq12 d12 row3 row3 row3 row3 g8_4 g8_4 row3 row3 row3 row3 83/e16 d13 dq13 d13 row4 row4 row4 row4 g8_5 g8_5 row4 row4 row4 row4 82/e15 d14 dq14 d14 row5 row5 row5 row5 g8_6 g8_6 row5 row5 row5 row5 81/c17 d15 dq15 a-1 d15 row6 row6 row6 row6 g8_7 g8_7 row6 row6 row6 row6 80/d16 0 a0 cld0 g8_0 (out) cld0 0 cld0 a0 a0 reserved cld0 reserved cld0 79/f14 0 a1 cld1 g8_1 (out) cld1 0 cld1 a1 a1 reserved cld1 reserved cld1 78/d15 0 a2 cld2 g8_2 (out) cld2 0 cld2 a2 a2 reserved cld2 reserved cld2 77/b17 0 a3 cld3 g8_3 (out) cld3 0 cld3 a3 a3 reserved cld3 reserved cld3 76/f13 0 a4 cld4 g8_4(out) cld4 0 cld4 a4 a4 reserved cld4 reserved cld4 75/e14 0 a5 cld5 g8_5 (out) cld5 0 cld5 a5 a5 reserved cld5 reserved cld5 74/c16 0 a6 cld6 g8_6 (out) cld6 0 cld6 a6 a6 reserved cld6 reserved cld6
pin description SPEAR300 32/69 doc id 16324 rev 1 73/a17 0 a7 cld7 g8_7 (out) cld7 0 cld7 a7 a7 reserved cld7 reserved cld7 72/b16 0 a8 cld8 it0 cld8 it0 cld8 it0 it0 reserved cld8 reserved cld8 71/d14 0 a9 cld9 it1 cld9 it1 cld9 it1 it1 reserved cld9 reserved cld9 70/c15 0 a10 cld10 it2 cld10 it2 cld10 it2 it2 reserved cld10 reserved cld10 69/a16 0 a11 cld11 it3 cld11 it3 cld11 it3 it3 reserved cld11 reserved cld11 68/b15 0 a12 cld12 it4 cld12 it4 cld12 it4 it4 reserved cld12 reserved cld12 67/c14 0 a13 cld13 it5 cld13 it5 cld13 it5 it5 reserved cld13 reserved cld13 66/e13 0 a14 cld14 it6 cld14 it6 cld14 it6 it6 reserved cld14 reserved cld14 65/b14 0 a15 cld15 it7 cld15 it7 cld15 it7 it7 reserved cld15 reserved cld15 64/d13 0 a16 cld16 spi_i2c4 cld16 spi_i2c4 cld16 spi_i2c4 spi_i2c4 reserved cld16 reserved cld16 63/c13 0 a17 cld17 spi_i2c5 cld17 spi_i2c5 cld17 spi_i2c5 spi_i2c5 reserved cld17 reserved cld17 62/a15 0 a18 cld18 spi_i2c6 cld18 spi_i2c6 cld18 spi_i2c6 spi_i2c6 reserved cld18 reserved cld18 61/e12 0 a19 cld19 spi_i2c7 cld19 spi_i2c7 cld19 spi_i2c7 /dout spi_i2c7 /dout reserved cld19 reserved cld19 60/a14 0 a20 cld20 tdm_ sync4 cld20 tdm_ sync4 cld20 tdm_ sync4 tdm_ sync4 reserved cld20 reserved cld20 59/b13 0 a21 cld21 tdm_ sync5 cld21 tdm_ sync5 cld21 tdm_ sync5 tdm_ sync5 reserved cld21 reserved cld21 58/d12 cl a22 cl tdm_ sync6 cld22 tdm_ sync6 cld22 tdm_ sync6 cl reserved cld22 reserved cld22 57/e11 al a23 al tdm_ sync7 cld23 tdm_ sync7 cld23 tdm_ sync7 al reserved cld23 reserved cld23 56/c12 /w /w /w row7 row7 row7 row7 /w /w row7 vsync_1 vsync_1 row7 55/a13 /r /g /r row8 row8 row8 row8 /r /r row8 hsync_1 hsync_1 row8 54/e10 0 0 clac g10_9 clac g10_9 clac g10_9 g10_9 g10_9 clac g10_9 clac 53/d11 0 0 clcp g10_8 clcp g10_8 clcp g10_8 g10_8 g10_8 clcp g10_8 clcp 52/b12 0 0 clfp g10_7 clfp g10_7 clfp g10_7 g10_7 g10_7 clfp g10_7 clfp table 10. pl_gpio pin description (continued) pl / pin number alternate function (enabled by ras register 1) configuration mode (enabled by ras register 2) 12345678910111213
SPEAR300 pin description doc id 16324 rev 1 33/69 51/d10 0 0 cllp g10_6 cllp g10_6 cllp g10_6 g10_6 g10_6 cllp g10_6 cllp 50/a12 tmr_cptr4 0 0 clle g10_5 clle g10_5 clle g10_5 g10_5 g10_5 clle g10_5 clle 49/c11 tmr_cptr3 0 0 clpp g10_4 clpp g10_4 clpp g10_4 g10_4 g10_4 clpp g10_4 clpp 48/b11 tmr_cptr2 b0 b0 cld22 spi_i2c0 spi_i2c0 spi_i2c0 spi_i2c0 spi_i2c0 spi_i2c0 spi_i2c0 dio4_1 dio4_1 spi_i2c0 47/c10 tmr_cptr1 b1 b1 cld23 spi_i2c1 spi_i2c1 spi_i2c1 spi_i2c1 spi_i2c1 spi_i2c1 spi_i2c1 dio5_1 dio5_1 spi_i2c1 46/a11 tmr_clk4 b2 b2 gpio7 spi_i2c2 spi_i2c2 spi_i2c2 spi_i2c2 spi_i2c2 spi_i2c2 spi_i2c2 dio6_1 dio6_1 spi_i2c2 45/b10 tmr_clk3 b3 b3 gpio6 spi_i2c3 spi_i2c3 spi_i2c3 spi_i2c3 spi_i2c3 spi_i2c3 spi_i2c3 dio7_1 dio7_1 spi_i2c3 44/a10 tmr_clk2 h0 h0 gpio5 g10_3/o0 g10_3/o0 g10_3/o0 g10_3/o0 g10_3 dac_o0 dac_o0 dac_o0 dac_o0 dac_o0 43/e9 tmr_clk1 h1 h1 gpio4 g10_2/o1 g10_2/o1 g10_2/o1 g10_2/o1 g10_2 dac_o1 dac_o1 dac_o1 dac_o1 dac_o1 42/d9 uart_dtr h2 h2 gpio3 i2s_din i2s_din i2s_din ai2s_din g10_1 i2s_din i2s_din i2s_din i2s_din i2s_din 41/c9 uart_ri h3 h3 gpio2 i2s_ lrck i2s_ lrck i2s_ lrck i2s_ lrck g10_0 i2s_lrck i2s_lrck i2s_lrck i2s_lrck i2s_lrck 40/b9 uart_dsr h4 h4 gpio1 i2s_clk i2s_clk i2s_clk i2s_clk tdm_syn c3 i2s_clk i2s_clk i2s_clk i2s_clk i2s_clk 39/a9 uart_dcd h5 h5 gpio0 i2s_ dout i2s_ dout i2s_ dout i2s_ dout tdm_syn c2 dout i2s_dout i2s_dout i2s_dout i2s_dout 38/a8 uart_cts h6 h6 tdm_ sync1 tdm_ sync1 tdm_ sync1 tdm_ sync1 tdm_ sync1 tdm_ sync1 tdm_ sync1 tdm_ sync1 tdm_ sync1 tdm_ sync1 tdm_ sync1 37/b8 uart_rts h7 h7 tdm_ dout tdm_ dout tdm_ dout tdm_ dout tdm_ dout tdm_ dout tdm_ dout tdm_ dout tdm_ dout tdm_ dout tdm_ dout 36/c8 ssp_cs4 0 0 tdm_ sync0 tdm_ sync0 tdm_ sync0 tdm_ sync0 tdm_ sync0 tdm_ sync0 tdm_ sync0 tdm_ sync0 tdm_ sync0 tdm_ sync0 tdm_ sync0 35/d8 ssp_cs3 reserved reserved tdm_clk tdm_clk tdm_clk tdm_clk tdm_clk tdm_clk tdm_clk tdm_clk tdm_clk tdm_clk tdm_clk 34/e8 ssp_cs2 0 0 tdm_din tdm_din tdm_din tdm_din tdm_ din tdm_din tdm_din tdm_din tdm_din tdm_din tdm_din 33/e7 basgpio5 0 0 sd_cmd sd_cmd sd_cmd sd_cmd sd _cmd sd_cmd sd_cmd sd_cmd sd_cmd sd_cmd sd_cmd 32/d7 basgpio4 0 0 sd_clk sd_clk sd_clk sd_clk sd _clk sd_clk sd_clk sd_clk sd_clk sd_clk sd_clk 31/c7 basgpio3 0 0 sd_dat0 sd_dat0 sd_dat0 sd_dat0 sd_dat0 sd_dat0 sd_dat0 sd_dat0 sd_dat0 sd_dat0 sd_dat0 30/b7 basgpio2 0 0 sd_dat1 sd_dat1 sd_dat1 sd_dat1 sd_dat1 sd_dat1 sd_dat1 sd_dat1 sd_dat1 sd_dat1 sd_dat1 table 10. pl_gpio pin description (continued) pl / pin number alternate function (enabled by ras register 1) configuration mode (enabled by ras register 2) 12345678910111213
pin description SPEAR300 34/69 doc id 16324 rev 1 29/a7 basgpio1 0 0 sd_dat2 sd_dat2 sd_dat2 sd_dat2 sd_dat2 sd_dat2 sd_dat2 sd_dat2 sd_dat2 sd_dat2 sd_dat2 28/a6 basgpio0 0 0 sd_sdat3 sd_sdat3 sd_sdat3 sd_sdat3 sd_s dat3 sd_sdat3 sd_sdat3 sd_sdat3 sd_sdat3 sd_sdat3 sd_sdat3 27/b6 mii_tx_clk 0 0 sd_sdat4 sd_sdat4 sd_sdat4 sd_sdat4 sd_sdat4 g8_0 g8_0 sd_sdat4 sd_sdat4 sd_sdat4 sd_sdat4 26/a5 mii_txd0 0 0 sd_sdat5 sd_sdat5 sd_sdat5 sd_sdat5 sd_sdat5 g8_1 g8_1 sd_sdat5 sd_sdat5 sd_sdat5 sd_sdat5 25/c6 mii_txd1 0 0 sd_sdat6 sd_sdat6 sd_sdat6 sd_sdat6 sd_sdat6 g8_2 g8_2 sd_sdat6 sd_sdat6 sd_sdat6 sd_sdat6 24/b5 mii_txd2 0 0 sd_sdat7 sd_sdat7 sd_sdat7 sd_sdat7 sd_sdat7 g8_3 g8_3 sd_sdat7 sd_sdat7 sd_sdat7 sd_sdat7 23/a4 mii_txd3 0 0 g8_4 g8_4 g8_4 g8_4 g8_4 g8_4 g8_4 g8_4 g8_4 g8_4 g8_4 22/d6 mii_tx_en 0 0 g8_5 g8_5 g8_5 g8_5 g8_5 g8_5 g8_5 g8_5 g8_5 g8_5 g8_5 21/c5 mii_tx_er 0 0 g8_6 g8_6 g8_6 g8_6 g8_6 g8_6 g8_6 dio7 dio8_1 dio8_1 dio7 20/b4 mii_rx_clk 0 0 g8_7 g8_7 g8_7 g8_7 g8_7 g8_7 g8_7 dio6 dio9_1 dio9_1 dio6 19/a3 mii_rx_dv 0 0 g10_0 g10_0 g10_0 g10_0 g10_0 g10_0 g10_0 dio5 dio10_1 dio10_1 dio5 18/d5 mii_rx_err 0 0 g10_1 g10_1 g10_1 g10_1 g10_1 g10_1 g10_1 dio4 dio11_1 dio11_1 dio4 17/c4 mii_rxd0 0 0 g10_2 g10_2 g10_2 g10_2 g10_2 g10_2 g10_2 dio3 dio12_1 dio12_1 dio3 16/e6 mii_rxd1 0 0 g10_3 g10_3 g10_3 g10_3 g10_3 g10_3 g10_3 dio2 dio13_1 dio13_1 dio2 15/b3 mii_rxd2 0 0 g10_4 g10_4 g10_4 g10_4 g10_4 g10_4 g10_4 dio1 g10_4 g10_4 dio1 14/a2 mii_rxd3 0 0 g10_5 g10_5 g10_5 g10_5 g10_5 g10_5 g10_5 dio0 g10_5 g10_5 dio0 13/a1 mii_col 0 0 g10_6 g10_6 g10_6 g10_6 g10_6 g10_6 g10_6 vsync g10_6 g10_6 vsync 12/d4 mii_crs 0 0 g10_7 g10_7 g10_7 g10_7 g10_7 g10_7 g10_7 hsync g10_7 g10_7 hsync 11/e5 mii_mdc 0 0 g10_8 g10_8 g10_8 g10_8 g10_8 g10_8 g10_8 g10_8 g10_8 g10_8 g10_8 10/c3 mii_mdio 0 0 g10_9 g10_9 g10_9 g10_9 g10_9 g10_9 g10_9 g10_9 g10_9 g10_9 g10_9 9/b2 ssp_mosi 0 0 sd_cd sd_cd sd_cd sd_cd sd_cd sd_cd sd_cd sd_cd sd_cd sd_cd sd_cd 8/c2 ssp_sclk 0 0 sd_wp sd_wp sd_wp sd_wp sd_wp sd_wp sd_wp sd_wp sd_wp sd_wp sd_wp 7/d3ssp_ss 000000000 0 0 0 0 6/b1 ssp_miso 0 0 sd_led sd_led sd_led sd_led sd_led sd_led sd_led sd_led sd_led sd_led sd_led 5/d2i2c_sda 000000000 0 0 0 0 table 10. pl_gpio pin description (continued) pl / pin number alternate function (enabled by ras register 1) configuration mode (enabled by ras register 2) 12345678910111213
SPEAR300 pin description doc id 16324 rev 1 35/69 4/c1i2c_scl 000000000 0 0 0 0 3/d1 uart_rx /e4 /e4 /e4111111 1 1 1 1 2/e4 uart_tx /e3 /e3 /e3111111 1 1 1 1 1/e3 irda_rx /e2 /e2 /e2111111 1 1 1 1 0/f3 irda_tx r/b r/b r/b1111 r/b r/b1111 ck1/k17 pl_clk1 tclk* tclk* cclk/ tclk* tclk* cclk/tcl k* tclk* cclk/ tclk* tclk* tclk* tclk* cclk/ tclk* tclk* cclk/ tclk* ck2/j17 pl_clk2 reserved reserved int_clk int_clk int_clk int _clk int_clk int_clk int_clk int_clk int_clk int_clk int_clk ck3/j16 pl_clk3 reserved reserved \int_clk \int_clk \int_clk \int_clk \int_clk \int_clk \int_clk clk clk clk clk ck4/h17 pl_clk4 reserved reserved 2.048 mhz 2.048 mhz 2.048 mhz 2.048 mhz 2.048 mhz 2.048 mhz 2.048 mhz pclk pclk pclk pclk table 10. pl_gpio pin description (continued) pl / pin number alternate function (enabled by ras register 1) configuration mode (enabled by ras register 2) 12345678910111213
pin description SPEAR300 36/69 doc id 16324 rev 1 notes/legend for ta bl e 1 0 : gpio (general purpose i/o): basgpio: base gpios in the basic subsystem g10 and g8: gpios in the telecom subsystem gpiox: gpios in the independent gpio block tdm_ : tdm interface signals sd_ : sdio interface it pins: interrupts table cells filled with ?0? or ?1? are unused and unless otherwise conf igured as alternate function or gpio, the corresponding pin is held at low or high level respectively by the internal logic. table cells filled with ?reserved? denote pins that must be left unconnected. table shading: fsmc fsmc pins: nand or nor flash keyboard keyboard pins rows are outputs, cols are inputs clcd color lcd controller pins camera camera pins
SPEAR300 memory mapping doc id 16324 rev 1 37/69 4 memory mapping table 11. memory mapping start address end address peripheral description 0x0000.0000 0x3fff.ffff external dram low power ddr or ddr2 0x4000.0000 0x4fff.ffff c3 0x5000.0000 0x5000.ffff telecom register 0x5001.0000 0x5001.0fff tdm action memory 0x5003.0000 0x5003.7fff tdm buffer memory 0x5004.0000 0x5004.0fff tdm sync memory 0x5005.0000 0x5005.0fff i2s i2s memory bank 1 0x5005.1000 0x5005.1fff i2s i2s memory bank 2 0x6000.0000 0x6fff.ffff clcd 0x7000.0000 0x7fff.ffff sdio 0x8000.0000 0x83ff.ffff static memory controller nand bank0 0x8400.0000 0x87ff.ffff static memory controller nand bank1 0x8800.0000 0x8bff.ffff static memory controller nand bank2 0x8c00.0000 0x8fff.ffff static memory controller nand bank3 0x9000.0000 0x90ff.ffff static memory controller nor bank0 0x9100.0000 0x91ff.ffff static memory controller nor bank1 0x9200.0000 0x91ff.ffff static memory controller nor bank2 0x9300.0000 0x93ff.ffff static memory controller nor bank3 0x9400.0000 0x98ff.ffff static memory controller register 0x9900.0000 0x9fff.ffff registers 0xa000.0000 0xa8ff.ffff keyboard 0xa900.0000 0xafff.ffff gpio 0xb000.0000 0xbfff.ffff - reserved 0xc000.0000 0xcfff.ffff - reserved 0xd000.0000 0xd007.ffff uart 0xd008.0000 0xd00f.ffff adc 0xd010.0000 0xd017.ffff spi 0xd018.0000 0xd01f.ffff i2c 0xd020.0000 0xd07f.ffff - reserved 0xd080.0000 0xd0ff.ffff jpeg codec 0xd100.0000 0xd17f.ffff irda 0xd180.0000 0xd1ff.ffff - reserved
memory mapping SPEAR300 38/69 doc id 16324 rev 1 0xd280.0000 0xd2ff.ffff sram static ram shared memory (8 kbytes) 0xd300.0000 0xe07f.ffff - reserved 0xe0800.0000 0xe0ff.ffff ethernet controller mac 0xe100.0000 0xe10f.ffff usb 2.0 device fifo 0xe110.0000 0xe11f.ffff usb 2.0 de vice configuration registers 0xe120.0000 0xe12f.ffff usb 2.0 device plug detect 0xe130.0000 0xe17f.ffff - reserved 0xe180.0000 0xe18f.ffff usb2.0 ehci 0-1 0xe190.0000 0xe19f.ffff usb2.0 ohci 0 0xe1a0.0000 0xe20f.ffff - reserved 0xe210.0000 0xe21f.ffff usb2.0 ohci 1 0xe220.0000 0xe27f.ffff - reserved 0xe280.0000 0xe28f.ffff ml u sb arb configuration register 0xe290.0000 0xe7ff.ffff - reserved 0xe800.0000 0xefff.ffff - reserved 0xf000.0000 0xf 00f.ffff timer 0xf010.0000 0xf10f.ffff - reserved 0xf110.0000 0xf11f.ffff itc primary 0xf120.0000 0xf7ff.ffff - reserved 0xf800.0000 0xfbff.ffff serial flash memory 0xfc00.0000 0xfc1f.ffff serial flash controller 0xfc20.0000 0xfc3f.ffff - reserved 0xfc40.0000 0xfc5f.ffff dma controller 0xfc60.0000 0xfc7f.ffff dram controller 0xfc80.0000 0xfc87.ffff timer 1 0xfc88.0000 0xfc8f.ffff watchdog timer 0xfc90.0000 0xfc97.ffff real-time clock 0xfc98.0000 0xfc9f.ffff general purpose i/o 0xfca0.0000 0xfca7.f fff system controller 0xfca8.0000 0xfcaf.ffff miscellaneous registers 0xfcb0.0000 0xfcb7.ffff timer 2 0xfcb8.0000 0xfcff.ffff - reserved 0xfd00.0000 0xfeff.ffff - reserved 0xff00.0000 0xffff.ffff internal rom boot table 11. memory mapping (continued) start address end address peripheral description
SPEAR300 electrical characteristics doc id 16324 rev 1 39/69 5 electrical characteristics 5.1 absolute minimum and maximum ratings this product contains devices to protect the in puts against damage due to high/low static voltages. however it is advisable to take normal precaution to avoid application of any voltage higher/lower than the specified maximum/minimum rated voltages. the absolute minimum and maximum rating is the maximum stress that can be applied to a device without causing permanent damage. however, extended exposure to minimum/maximum ratings may affe ct long-term device reliability. the average chip-junction temperature, t j , can be calculated using the following e q uation: t j = t a + (p d ? ja ) where: t a is the ambient temperature in c ja is the package junction-to-ambient thermal resistance, which is 34 c/w p d = p int + p port ? p int is the chip internal power ? p port is the power dissipation on input and output pins, user determined if p port is neglected, an approximate relationship between p d is: p d = k / (t j + 273 c) and, solving first e q uations: k = p d ? (t a + 273 c) + ja x p d 2 k is a constant for the particular case, which can be determined through last e q uation by measuring p d at e q uilibrium, for a known t a . using this value of k, the value of p d and t j can be obtained by solving first and second e q uation, iteratively for any value of t a . table 12. absolute minimum and maximum ratings symbol parameter minimum value maximum value unit v dd 1.2 supply voltage for the core - 0.3 1.6 v v dd 3.3 supply voltage for the i/os - 0.3 4.8 v v dd 2.5 supply voltage for the analog blocks - 0.3 4.8 v v dd 1.8 supply voltage for the dram interface - 0.3 4.8 v t j junction temperature -40 125 c t stg storage temperature -55 150 c
electrical charac teristics SPEAR300 40/69 doc id 16324 rev 1 5.2 maximum power consumption note: the s e value s take into con s ideration the wor s t ca s e s of proce ss variation and voltage range and mu s t be u s ed to de s ign the power s upply s ection of the board. the maximum current and power values listed above are not guaranteed to be the highest obtainable. these values are dependent on many factors including the type of applications running, clock rates, use of internal functional capabilities, external interface usage, case temperature, and the power supply voltages. your specific application can produce significantly different results. 1.2 v current and power are primarily dependent on the applications running and the use of internal chip functions (dma, usb, ethernet, and so on). 3.3 v current and power are primarily dependent on the capacitive loading, fre q uency, and utilization of the external buses. 5.3 dc electrical characteristics the recommended operating conditions are listed in the following table: table 13. maximum power consumption symbol description max unit v dd 1.2 supply voltage for the core (1) 1. peak current with cpu at maximum speed in asynchronous mode with ddr at maximum speed. 420 ma v dd 1.8 supply voltage for the dram interface (2) 2. peak current with linux memory test (50% write and 50% read) plus dma reading memory. 160 ma v dd 2.5 supply voltage for the analog blocks 35 ma v dd 3.3 supply voltage for the i/os (3) 3. with 30 logic channels connected to the dev ice and simultaneously switching at 10 mhz. 15 ma p d maximum power consumption 930 mw table 14. recommended operating conditions symbol parameter min typ max unit v dd core supply voltage for the core 1.14 1.2 1.26 v v dd i/o supply voltage for the i/os 3 3.3 3.6 v v dd pll pll supply voltage 2.25 2.5 2.75 v v dd osc oscillator supply voltage 2.25 2.5 2.75 v v dd 1.8 supply voltage for dram interface 1.7 1.8 1.9 v
SPEAR300 electrical characteristics doc id 16324 rev 1 41/69 5.4 overshoot and undershoot this product can support the following values of overshoot and undershoot. table 1. if the amplitude of the overshoot/undershoo t increases (decreases), the ratio of overshoot/undershoot width to the pulse width decreases (increases). the formula relating the two is: amplitude of os/us = 0.75*(1- ratio of os (or us) duration with respect to pulse width) note: the value of over s hoot/under s hoot s hould not exceed the value of 0.5 v. however, the duration of the over s hoot/under s hoot can be increa s ed by decrea s ing it s amplitude. 5.5 general purpose i/o characteristics the 3.3 v i/os are compliant with jedec standard jesd8b v dd rtc rtc supply voltage 1.2 1.5 1.8 v t a operating temperature -40 85 c table 14. recommended operating conditions (continued) symbol parameter min typ max unit table 15. overshoot and undershoot specifications parameter 3v3 i/os 2v5 i/os 1v8 i/os amplitude 500 mv 500 mv 500 mv ratio of overshoot (or unders hoot) duration with respect to pulse width 1/3 1/3 1/3 table 16. low voltage ttl dc input specification (3 v< v dd <3.6 v) symbol parameter min max unit v il low level input voltage 0.8 v v ih high level input voltage 2 v v hyst schmitt trigger hysteresis 300 800 mv table 17. low voltage ttl dc output specification (3 v< v dd <3.6 v) symbol parameter test condition min max unit v ol low level output voltage i ol = x ma (1) 1. for the max current value (x ma) refer to section 3: pin de s cription . 0.3 v v oh high level output voltage i oh = -x ma (1) v dd - 0.3 v
electrical charac teristics SPEAR300 42/69 doc id 16324 rev 1 5.6 lpddr and ddr2 pin characteristics 5.6.1 ddr2 timing characteristics the characterization timing is done considering an output load of 10 pf on all the ddr pads. the operating conditions are in worst case v = 0.90 v t a = 125 c and in best case v=1.10 v t a = 40 c. table 18. pull-up and pull-down characteristics symbol parameter test condition min max unit r pu e q uivalent pull-up resistance v i = 0 v 29 67 k r pd e q uivalent pull-down resistance v i = v dde 3v3 29 103 k table 19. dc characteristics symbol parameter test condition min max unit v il low level input voltage sstl2 -0.3 v ref -0.15 v sstl18 -0.3 v ref -0.125 v v ih high level input voltage sstl2 v ref +0.15 v dde 2v5+0.3 v sstl18 v ref +0.125 v dde 1v8+0.3 v v hyst input voltage hysteresis 200 mv table 20. driver characteristics symbol parameter min typ max unit r o output impedance 45 table 21. on die termination symbol parameter min typ max unit rt1* termination value of resistance for on die termination 75 rt2* termination value of resistance for on die termination 150 table 22. reference voltage symbol parameter min typ max unit v refin voltage applied to core/pad 0.49 * v dde 0.500 * v dde 0.51 * v dde v
SPEAR300 electrical characteristics doc id 16324 rev 1 43/69 ddr2 read cycle timings figure 3. read cycle waveforms figure 4. read cycle path table 23. read cycle timings frequency t4 max t5 max t5 max 333 mhz 1.24 ns -495 ps -495 ps 266 mhz 1.43 ns -306 ps -306 ps 200 mhz 1.74 ns 4 ps 4 ps 166 mhz 2.00 ns 260 ps 260 ps 133 mhz 2.37 ns 634 ps 634 ps t4 t5 t5 t4 t4 dqs dq t3 t1 t2 dll d q q clr set dq dqs
electrical charac teristics SPEAR300 44/69 doc id 16324 rev 1 ddr2 write cycle timings figure 5. write cycle waveforms figure 6. write cycle path table 24. write cycle timings frequency t4 max t5 max unit 333 mhz 1.36 -1.55 ns 266 mhz 1.55 -1.36 ns 200 mhz 1.86 -1.05 ns 166 mhz 2.11 - 794 ns 133 mhz 2.49 -420 ns t6 t6 t6 t4 t5 t4 t5 t4 t5 clk dqs dq
SPEAR300 electrical characteristics doc id 16324 rev 1 45/69 ddr2 command timings figure 7. command waveforms figure 8. command path 5.7 clcd timing characteristics the characterization timing is done considering an output load of 10 pf on all the outputs.the operating conditions are in worst case v=0.90 v t=125 c and in best case v =1.10 v t= 40 c. the clcd has a wide variety of configurations and setting and the parameters change accordingly. two main scenarios will be consid ered, one with direct cl ock to output (166 mhz), setting bcd bit to '1', and the second one with the clock passing through a clock divider (83 mhz), setting bcd bit to '0'. table 25. command timings frequency t4 max t5 max unit 333 mhz 1.39 1.40 ns 266 mhz 1.77 1.78 ns 200 mhz 2.39 2.40 ns 166 mhz 2.90 2.91 ns 133 mhz 3.65 3.66 ns t4 t5 clk address, strobes, and control lines
electrical charac teristics SPEAR300 46/69 doc id 16324 rev 1 5.7.1 clcd timing charact eristics direct clock figure 9. clcd waveform with clcp direct figure 10. clcd block diagram with clcp direct note: 1 t stable = t clock direct max - (t max + t min ) 2for t ma x the maximum value i s taken from the wor s t ca s e and be s t ca s e, while for t min the minimum value i s taken from the wor s t ca s e and be s t ca s e. 3clcp s hould be delayed by {t max + [t clock direct max - (t max + t min )]/2} = 4.7915 n s table 26. clcd timings with clcp direct parameter value frequency t clock direct max (t clock ) 6 ns 166 mhz t clock direct max rise (t r ) 0.81 ns t clock direct max (t f ) 0.87 ns t min -0.04 ns t max 3.62 ns t stable 2.34 ns tmin tmax clcp cld[23:0],clac,clle,cllp, clfp ,c lpow er tc loc k tr tf tstable q q set cl r d t2 t3 clcp cld[23:0],clac,clle, cllp,clfp,clpower clcdclk t1
SPEAR300 electrical characteristics doc id 16324 rev 1 47/69 5.7.2 clcd timing char acteristics divided clock figure 11. clcd waveform with clcp divided figure 12. clcd block diagram with clcp divided table 105. note: 1 t stable = t clock direct max - (tmax + tmin) 2for t max the maximum value i s taken from the wor s t ca s e and for t min the minimum value i s taken from the be s t ca s e. 3clcp s hould be delayed by {t max + [t clock direct max - (t max + t min )]/2} = 6.945 n s table 27. clcd timings with clcp divided parameter value frequency t clock divided max 12 ns 83.3 mhz t clock divided max rise (t r ) 0.81 ns t clock divided max (t f ) 0.87 ns t min -0.49 ns t max 2.38 ns t stable 9.13 ns tmin tmax clcp cld[23:0],clac,clle,cllp, clfp ,c lpow er tc loc k tr tf tstable q q set cl r d t2 clcp cld[23:0],clac,clle, cllp,clfp,clpower clcdclk t1 q q set cl r d t3
electrical charac teristics SPEAR300 48/69 doc id 16324 rev 1 5.8 i 2 c timing characteristics the characterization timing is done using primetime considering an output load of 10 pf on scl and sda. the operating conditions are v = 0.90 v, t a =125 c in worst case and v =1. 10 v, t a = 40 c in best case. figure 13. i 2 c output pins figure 14. i 2 c input pins the flip-flops used to capture the incoming si gnals are re-synchronized with the ahb clock: so, no input delay calculation is re q uired. those values are referred to the common internal source clock which has a period of: t hclk = 6 ns. table 28. output delays for i 2 c signals parameter min max unit t hclk -> sclh 8.1067 11.8184 ns t hclk -> scll 7.9874 12.6269 ns t hclk -> sdah 7.5274 11.2453 ns t hclk -> sdal 7.4081 12.0530 ns set q q d clr set q q d clr hclk scl sda
SPEAR300 electrical characteristics doc id 16324 rev 1 49/69 figure 15. output signal waveforms for i 2 c signals the timing of high and low level of scl (t sclhigh and t scllow ) are programmable. table 29. time characteristics for i 2 c in high-speed mode parameter min unit t su-sta 157.5897 ns t hd-sta 325.9344 t su-dat 314.0537 t hd-dat 0.7812 t su-sto 637.709 t hd-sto 4742.1628 table 30. time characteristics for i 2 c in fast speed mode parameter min unit t su-sta 637.5897 ns t hd-sta 602.169 t su-dat 1286.0537 t hd-dat 0.7812 t su-sto 637.709 t hd-sto 4742.1628 table 31. time characteristics for i 2 c in standard speed mode parameter min unit t su-sta 4723.5897 ns t hd-sta 3991.9344 t su-dat 4676.0537 t hd-dat 0.7812 t su-sto 4027.709 t hd-sto 4742.1628
electrical charac teristics SPEAR300 50/69 doc id 16324 rev 1 note: 1 the timing s s hown in figure 15. depend on the programmed value of t sclhigh and t scllow, s o the value s pre s ent in the three table s here above have been calculated u s ing the minimum programmable value s of : ic_hs_scl_hcnt=19 and ic_hs_scl_lcnt=53 regi s ter s (for high-speed mode); ic_fs_scl_hcnt=99 and ic _fs_scl_lcnt=215 regi s ter s (for fa s t-speed mode); ic_ss_scl_hcnt=664 and ic_ss_scl_lcnt=780 regi s ter s (for standard-speed mode). the s e minimum value s depend on the ahb clock frequency, which i s 166 mhz. 2 a device may internally requi re a hold time of at lea s t 300 n s for the sda s ignal (referred to the v ihmin of the scl s ignal) to bridge the undefined region of t he falling edge of scl (plea s e refer to the i 2 c bu s specification v3-0 jun 2007). however, the sda data hold time in the i 2 c controller of SPEAR300 i s one-clock cycle ba s ed (6 n s with the hclk clock at 166 mhz). thi s time may be in s ufficient for s ome s lave device s . a few s lave device s may not receive the valid addre ss due to the lack of sda hold ti me and will not acknowledge even if the addre ss i s valid. if the sda data hold time i s in s ufficient, an error may occur. 3 workaround: if a device need s more sda data hold time than one clock cycle, an rc delay circuit i s needed on the sda line a s illu s trated in the following figure: figure 16. rc delay circuit for example, r=k and c = 200 pf. 5.9 fsmc timing characteristics the characterization timing is done using prim etime considering an output load of 3pf on the data, 15pf on nf_ce, nf_re and nf_we and 10pf on nf_ale and nf_cle. the operating conditions are v=0.90v, t=125c in worst case and v=1.10v, t= 40c in best case.
SPEAR300 electrical characteristics doc id 16324 rev 1 51/69 5.9.1 8-bit nand flash configuration figure 17. output pads for 8-bit nand flash configuration figure 18. input pads for 8-bit nand flash configuration figure 19. output command si gnal waveforms for 8-bit nand flash configuration set q q d clr set q q d clr hclk nfcle nfce nfwe nfre nfrwprt nfale nfio_0..7 set q q d clr set q q d clr nfrb nfio_0..7 clpower cllp clle clfp clcp clac cld_23..22 (nfio_8..15) hclk nfcle nf ce nfwe nfio command t cle t we t io
electrical charac teristics SPEAR300 52/69 doc id 16324 rev 1 figure 20. output address signal waveforms for 8-bit nand flash configuration figure 21. in/out data address signal waveforms for 8-bit nand flash configuration note: value s in ta b l e 3 2 are referred to the common internal s ource clock which ha s a period of thclk = 6 n s . table 32. time characteristics fo r 8-bit nand flash configuration parameter min max unit t cle -16.85 -19.38 ns t ale -16.84 -19.37 t we (s=1) 11.10 13.04 t re (s=1) 11.18 13.05 t io (h=1) 3.43 8.86 nf ale nfc e nfwe nfio address t ale t we t io nfce nfwe nf i o (out ) data out t io nf i o (i n) nfre t re? io t we t re t read t nfio? ffs
SPEAR300 electrical characteristics doc id 16324 rev 1 53/69 5.9.2 16-bit nand flash configuration figure 22. output pads for 16 -bit nand flash configuration figure 23. input pads for 16-bit nand flash configuration figure 24. output command signal waveforms 16-bit nand flash configuration set q q d clr set q q d clr hclk nfcle nfce nfwe nfre nfrwprt nfale nfio_0..7 clpower cllp clle clfp clcp clac cld_23..22 (nfio_8..15) set q q d clr set q q d clr nfrb nfio_0..7 clpower cllp clle clfp clcp clac cld_23..22 (nfio_8..15) hclk nfcle nf ce nfwe nfio command t cle t we t io
electrical charac teristics SPEAR300 54/69 doc id 16324 rev 1 figure 25. output address signal waveforms 16-bit nand flash configuration figure 26. in/out data si gnal waveforms for 16-bit nand flash configuration note: value s in ta b l e 3 3 are referred to the common internal s ource clock which ha s a period of thclk = 6 n s . 5.10 ether mac 10/100/1000 mbps (gmac-univ) timing characteristics the characterization timing is given for an output load of 5 pf on the gmii tx clock and 10 pf on the other pads. the operating conditions are in worst case v=0.90 v t=125 c and in best case v=1.10 v t= 40 c. table 33. time characteristics for 16-bit nand flash configuration parameter min max unit t cle -16.85 -19.38 ns t ale -16.84 -19.37 t we (s=1) 11.10 13.04 t re (s=1) 11.18 13.05 t io (h=1) 3.27 11.35 nfale nf ce nfwe nfio address t al e t we t io nfce nfwe nfio (out) data out t io nfio (in) nfre t re? io t we t re t r ead t nfio? ffs
SPEAR300 electrical characteristics doc id 16324 rev 1 55/69 5.10.1 gmii transmit timing specifications figure 27. gmii tx waveforms figure 28. block diagram of gmii tx pins note: to calculate the t setup value for the phy you have to con s ider the next t clk ri s ing edge, s o you have to apply the following formula: t setup = t clk - t max table 34. gmii tx timing parameter value using gmii [t clk period = 8 ns 125 mhz] t rise (t r ) <1 ns t fall (t f ) <1 ns t max = t2 max - t3 min 2.8 ns t min = t2 min - t3 max 0.4 ns t setup 5.19 ns tm in tm ax gmiitx _clk txd0-txd3 , gmiitx_d4-gmiitx _d7, tx_en , tx_er tclock tr tf q q set cl r d t2 t3 gmiitx_clk tx[0..3], gmii_tx[4..7], tx_en, tx_er clk tx[0..3], gmii_tx[4..7], tx_en, tx_er
electrical charac teristics SPEAR300 56/69 doc id 16324 rev 1 5.10.2 mii transmit timing specifications figure 29. mii tx waveforms figure 30. block diagram of mii tx pins note: to calculate the t setup value for the phy you have to con s ider the next t clk ri s ing edge, s o you have to apply the following formula: t setup = t clk - t max table 35. mii tx timings parameter value using mii 10 mb [t clk period = 40 ns 25 mhz] value using mii 100 mb [t clk period = 400 ns 2.5 mhz] t max = t2 max - t3 min 6.8 ns 6.8 ns t min = t2 min - t3 max 2.9 ns 2.9 ns t setup 33.2 ns 393.2 ns tm in tm ax tx_c lk txd0 -t xd 3 tclock tr tf q q set cl r d t2 t3 tx_clk txd[0..3] tx[0..3]
SPEAR300 electrical characteristics doc id 16324 rev 1 57/69 5.10.3 gmii-mii receive timing specifications figure 31. gmii-mii rx waveforms figure 32. block diagram of gmii-mii rx pins note: the input s tage i s the s ame for all the interface s (gmii and mii10/100) s o t setup and t hold value s are equal in all the ca s e s . the receive path i s optimized for the gmii interface: thi s al s o en s ure s correct capture of data for the mii10/100 interface. 5.10.4 mdio timing specifications figure 33. mdc waveforms ts th rx _c lk rxd0-rxd3, gm iirx_d 4- gm iir x_d7, rx_er, rx_d v tc loc k tr tf t1 q q set cl r d t2 rx[0.. 3], gmii_ rx[4.. 7] , rx_er, rx_dv rx_clk input thold mdc mdio tc loc k tr tf ou tp ut tsetup tmin tmax
electrical charac teristics SPEAR300 58/69 doc id 16324 rev 1 figure 34. paths from mdc/mdio pads note: when mdio i s u s ed a s output the data are launched on the falling edge of the clock a s s hown in figure 33 . table 36. mdc/mdio timing parameter value frequency t clk period 614.4 ns 1.63 mhz t clk fall (t f ) 1.18 ns t clk rise (t r ) 1.14 ns output t max = ~t clk /2 307 ns t min = ~t clk /2 307 ns input t setupmax = t1 max - t3 min 6.88 ns t holdmin = t1 min - t3 max -1.54 ns q q set cl r d t2 t3 clk md io t1 q q set cl r d md c input output
SPEAR300 electrical characteristics doc id 16324 rev 1 59/69 5.11 smi - serial memory interface figure 35. smidatain data path figure 36. smidataout/smicsn data paths table 37. smidatain timings signal parameter value smi_datain t d_max t smidatain_arrival_max - t input_delay t d_min t smidatain_arrival_min - t input_delay t cd_min t smi_clk_i_arrival_min t cd_max t smi_clk_i_arrival_max t setup_max t s + t d_max -t cd_min t hold_min t h - t d_min + t cd_max hclk smi_clk smi_datain smi_clk_i t smidatain arrival t input_delay t d t h t s t cd hclk hclk output smiclk
electrical charac teristics SPEAR300 60/69 doc id 16324 rev 1 figure 37. smidataout timings figure 38. smicsn fall timings table 38. smidatain timings signal parameter value smi_dataout t delay_max t arrivalsmidataout_max - t arrival_smi_clk_min t delay_min t arrivalsmidataout_min - t arrival_smi_clk_max table 39. smicsn fall timings signal parameter value smi_csn fall t delay_max t arrivalsmicsn_max_fall - t arrival_smi_clk_min_fall t delay_min t arrivalsmicsn_min_fall - t arrival_smi_clk_max_fall smi_clk smidataout(fast) t delay_min t arrival smidataout(slow) t delay_max
SPEAR300 electrical characteristics doc id 16324 rev 1 61/69 figure 39. smicsn rise timings 5.12 spi this module provides a programmable le ngth shift register which allows serial communication with other spi devices through a 3 or 4 wire interface (spi_sck, miso, mosi and spi_csn). table 40. smicsn rise timings signal parameter value smi_csn rise t delay_max t arrivalsmicsn_max_rise - t arrival_smi_clk_min_fall t delay_min t arrivalsmicsn_min_rise - t arrival_smi_clk_max_fall table 41. timing requirements for smi parameter input setup-hold/output delay max min smi_clk fall time 1.8209 1.4092 rise time 1.6320 1.1959 smidatain input setup time 8.27482 input hold time -2.595889 smidataout output valid time 2.039774 smics_0 output valid time fall 1.922779 rise 1.69768 smics_1output valid time fall 1.7898169 rise 1.638069
electrical charac teristics SPEAR300 62/69 doc id 16324 rev 1 figure 40. spi_clk timings 5.12.1 spi master mode timings (clock phase = 0) figure 41. spi master mode external timing (clock phase =0) table 42. spi timing requirements (all modes) no. parameters min max unit 1t c(clk) cycle time, spi_sck 24 ns 2t w(clkh) pulse duration, spi_sck high 0.49*t c(clk) - 0.51*t c(clk) ns 3t w(clkl) pulse duration, spi_sck low 0.51t c(clk) - 0.49*t c(clk) ns
SPEAR300 electrical characteristics doc id 16324 rev 1 63/69 5.12.2 spi master mode timings (clock phase = 1) figure 42. spi master mode external timing (clock phase = 1) table 43. timing requirements for spi master mode [clock phase = 0] no. parameters max. unit 4t su(div-clkl) setup time, miso (input) valid before spi_sck (output) falling edge clock polarity = 0 11.832 ns 5t su(div-clkh) setup time, miso (input) valid before spi_sck (output) rising edge clock polarity = 1 11.950 ns 6t h(clkl-div) hold time, miso (input)valid after spi_sck (output) falling edge clock polarity = 0 -7.690 ns 7t h(clkh-div) hold time, miso (input) valid after spi_sck (output) rising edge clock polarity = 1 -7.958 ns table 44. switching characteristics over recommen ded operating conditions for spi master mode (clock phase = 0) no. parameters max unit 8t d(clkh-dov) delay time, spi_sck (output) rising edge to mosi (output) transition clock polarity = 0 1.960 ns 9t d(clkl-dov) delay time, spi_sck (output) falling edge to mosi (output) transition clock polarity = 1 21.75 ns 10 t d(enl-clkh/l) delay time, spi_csn (output) falling edge to first spi_sck (output) rising or falling edge tns 11 t d(clkh/l-enh) delay time, spi_sck (output) rising or falling edge to spi_csn (output) rising edge t/2 ns
electrical charac teristics SPEAR300 64/69 doc id 16324 rev 1 table 45. timing requirements for spi master mode (clock phase = 1) no. parameters max unit 12 t su(div-clkl) setup time, miso (input) valid before spi_sck (output) rising edge clock polarity = 0 11.950 ns 13 t su(div-clkh) setup time, miso (input) valid before spi_sck (output) falling edge clock polarity = 1 11.832 ns 14 t h(clkl-div) hold time, miso (input) valid after spi_sck (output) rising edge clock polarity = 0 -7.958 ns 15 t h(clkh-div) hold time, miso (input) valid after spi_sck (output) falling edge clock polarity = 1 -7.690 ns table 46. switching characteristics over recommended operating conditions for spi master mode (clock phase =1 ) no. parameters max unit 16 t d(clkh-dov) delay time, spi_sck (output) rising edge to mosi (output) transition clock polarity = 0 1.960 ns 17 t d(clkl-dov) delay time, spi_sck (output) falling edge to mosi (output) transition clock polarity = 1 2.175 ns 18 t d(enl- clkh/l) delay time, spi_csn (output) falling edge to first spi_sck (output) rising or falling edge t/2 ns 19 t d(clkh/l- enh) delay time, spi_sck (output) rising or falling edge to spi_csn (output) rising edge tns
SPEAR300 electrical characteristics doc id 16324 rev 1 65/69 5.13 uart (universal asynchro nous receiver/transmitter) figure 43. uart transmit and receive timings where (1) b = uart baud rate 5.14 power up sequence the only re q uirement is that the various power supplies reach the correct range in less than 10 ms. 5.15 power on reset (mreset) the mreset must remain active for at least 10 ms after all the power supplies are in the correct range and should become active in no more than 10 s when one of the power supplies goes out of the correct range. table 47. uart transmit timing characteristics s.no. parameters min max unit 1 uart maximum baud rate 3 mbps 2 uart pulse duration transmit data (txd) 0.99b (1) b (1) ns 3 uart transmit start bit 0.99b (1) b (1) ns table 48. uart receive timing characteristics s.no. parameters min max units 4 uart pulse duration receive data (rxd) 0.97b (1) 1.06b (1) ns 5 uart receive start bit 0.97b (1) 1.06b (1) ns
package information SPEAR300 66/69 doc id 16324 rev 1 6 package information in order to meet environmental re q uirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www. s t.com . ecopack ? is an st trademark. table 49. lfbga289 (15 x 15 x 1.7 mm) mechanical data dim. mm inches min. typ. max. min. typ. max. a 1.700 0.0669 a1 0.270 0.0106 a2 0.985 0.0387 a3 0.200 0.0078 a4 0.800 0.0315 b 0.450 0.500 0.550 0.0177 0.0197 0.0217 d 14.850 15.000 15.150 0.5846 0.5906 0.5965 d1 12.800 0.5039 e 14.850 15.000 15.150 0.5846 0.5906 0.5965 e1 12.800 0.5039 e 0.800 0.0315 f 1.100 0.0433 ddd 0.200 0.0078 eee 0.150 0.0059 fff 0.080 0.0031
SPEAR300 package information doc id 16324 rev 1 67/69 figure 44. lfbga289 package dimensions
revision history SPEAR300 68/69 doc id 16324 rev 1 7 revision history table 50. document revision history date revision changes 15-oct-2009 1 initial release.
SPEAR300 doc id 16324 rev 1 69/69 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorized st representative, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2009 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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